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cmos 8-bit single-chip microcomputer description the cxp85112b/85116b, cxp85220a/85224a/ 85228a/85232a is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, vector interruption, on-screen display function, i 2 c bus interface, pwm generator, remote control reception circuit, hsync counter, power source frequency counter and watch dog timer besides the basic configurations of 8-bit cpu, rom, ram, and l/o port. the cxp85112b/85116b, cxp85220a/85224a/ 85228a/85232a also provides a power-on reset function and a sleep function that enables lower power consumption. features wide-range instruction system (213 instructions) to cover various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 1s at 4mhz operation incorporated rom capacity 12k bytes (cxp85112b) 16k bytes (cxp85116b) 20k bytes (cxp85220a) 24k bytes (cxp85224a) 28k bytes (cxp85228a) 32k bytes (cxp85232a) incorporated ram capacity 352 bytes (cxp85112b/85116b) 448 bytes (cxp85220a/85224a/85228a/85232a) peripheral functions ?on-screen display function 12 16 dots, 128 types 21 words 4 iines (more than 4 iines possible) double scan mode compatible, jitter elimination circuit ?i 2 c bus interface ?pwm output 14 bits, 1 channel 6 bits, 8 channels ?remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage fifo ?a/d converter 4 bits, 4channels, successive approximation method (conversion time of 40s/4mhz) ?hsync counter ?power supply frequency counter ?watch dog timer ?serial i/o 8-bit clock synchronization ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer interruption 14 factors, 14 vectors, multi-interruption possible standby mode sleep package 64-pin plastic sdip/qfp piggyback/evaluation chip cxp85100a, cxp85190 (custom font compatible) cxp85200a, cxp85290 (custom font compatible) ?1 e93z17b86 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp85112b/85116b cxp85220a/85224a/85228a/85232a 64 pin sdip (plastic) 64 pin qfp (plastic) structure silicon gate cmos ic purchase of sony's i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips.
? 2 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a o n s c r e e n d i s p l a y s e r i a l i / o t i m e r / c o u n t e r r e m o c o n f i f o h s y n c c o u n t e r a c t i m e r a / d c o n v e r t e r i 2 c i n t e r f a c e u n i t w a t c h d o g t i m e r 1 4 b i t p w m 6 b i t p w m 8 c h c l o c k g e n . / s y s t e m c o n t r o l r a m 3 5 2 / 4 4 8 b y t e s s p c 7 0 0 c p u c o r e p r e s c a l e r / t i m e b a s e t i m e r p o r t a p o r t b p o r t c p o r t d p o r t e p o r t f 2 2 v s s v d d m p x t a l e x t a l r s t p f 0 / p w m 0 t o p f 7 / p w m 7 i n t e r r u p t c o n t r o l l e r p a 0 t o p a 7 p b 0 t o p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 5 p e 6 t o p e 7 p f 0 t o p f 7 x l c b r b l k h s y n c v s y n c p d 3 / s i p d 2 / s o p d 1 / s c k p d 7 / e c p e 7 / t o p d 6 / r m c p d 4 / h s i p d 5 / a c i p e 2 / a n 0 t o p e 5 / a n 3 p f 4 / s c l 0 p f 5 / s c l 1 p f 6 / s d a 0 p f 7 / s d a 1 p e 6 / p w m p e 0 / i n t 0 p e 1 / i n t 1 p d 0 / i n t 2 g e x l c r o m 1 2 k / 1 6 k / 2 0 k / 2 4 k / 2 8 k / 3 2 k b y t e s block diagram
? 3 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a v d d n c v s s m p p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 p f 3 / p w m 3 b l k r g b v s y n c h s y n c e x l c x l c p e 0 / i n t 0 p e 1 / i n t 1 p e 2 / a n 0 p e 3 / a n 1 p e 4 / a n 2 p e 5 / a n 3 p e 6 / p w m p e 7 / t o r s t e x t a l x t a l p d 0 / i n t 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 6 1 6 3 6 4 6 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 p f 4 / p w m 4 / s c l 0 p f 5 / p w m 5 / s c l 1 p f 6 / p w m 6 / s d a 0 p f 7 / p w m 7 / s d a 1 p a 7 p a 6 p a 5 p a 4 p a 3 p a 2 p a 1 p a 0 p b 7 p b 6 p b 5 p b 4 p b 3 p b 2 p b 1 p b 0 p c 7 p c 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 p d 7 / e c p d 6 / r m c p d 5 / a c i p d 4 / h s i p d 3 / s i p d 2 / s o p d 1 / s c k v s s 4 5 6 7 8 9 1 0 2 3 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 note) 1. nc (pin 63) must be connected to v dd . 2. vss for both pins 32 and 62 must be grounded. 3. mp (pin 61) must be connected to gnd. pin assignment 1 (top view) 64 pin sdip package
? 4 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a p f 3 / p w m 3 b l k r g b v s y n c h s y n c e x l c 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 6 1 6 3 6 4 6 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 p f 4 / p w m 4 / s c l 0 p f 5 / p w m 5 / s c l 1 p f 6 / p w m 6 / s d a 0 p f 7 / p w m 7 / s d a 1 p b 7 p b 6 p b 5 p b 4 p b 3 p b 2 p b 1 p b 0 p c 7 p c 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 p d 7 / e c 4 5 6 7 8 9 1 0 2 3 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 p a 2 p a 3 p a 4 p a 5 p a 7 v s s p a 6 v d d n c m p p f 0 / p w m 0 p f 2 / p w m 2 p f 1 / p w m 1 p a 1 p a 0 p d 6 / r m c p d 5 / a c i p d 4 / h s i p d 3 / s i p d 1 / s c k v s s p d 2 / s o p d 0 / i n t 2 x t a l e x t a l r s t p e 6 / p w m p e 7 / t o 3 1 3 2 x l c p e 0 / i n t 0 p e 1 / i n t 1 p e 2 / a n 0 p e 3 / a n 1 p e 4 / a n 2 p e 5 / a n 3 note) 1. nc (pin 56) must be connected to v dd . 2. vss for both pins 26 and 58 must be grounded. 3. mp (pin 55) must be connected to gnd. pin assignment 2 (top view) 64 pin qfp package
? 5 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a (port a) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port b) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port d) 8-bit i/o port. i/o can be set ina a unit of single bits. capable of driving 12ma sink current. (8 pins) (port e) 8-bit port. lower 6 bits are for inputs; upper 2 bits are for outputs. (port f) 8-bit output port, operating as n-ch open drain output for high current (12ma). lower 4 bits are medium voltage drive outputs (12v), upper 4bits are 5v drive outputs. (8 pins) 4-bit outputs for crt display. horizontal synchronizing signal input for crt display. vertical synchronizing signal input for crt display. pin description symbol pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hsi pd5/aci pd6/rmc pd7/ec pe0/int0 pe1/int1 pe2/an0 to pe5/an3 pe6/pwm pe7/to pf0/pwm0 to pf3/pwm3 pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 r, g, b, blk hsync vsync i/o i/o i/o i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input input/input input/input output/output output/output output/output output/output/ i/o output/output/ i/o output input input i/o description external interruption request input. active at falling edge. serial clock i/o. serial data output. serial data input. hsync counter input. input for power supply frequency counter. input for remote control reception circuit. external event input for timer/counter. external interruption request inputs. active at falling edge. (2 pins) analog inputs for a/d converter. (4 pins) 14-bit pwm output. (cmos output) rectangular waveform output for timer 1. (duty output 50%) 6-bit pwm outputs. (8 pins) transfer clock i/os for i 2 c bus interface. transfer data i/os for i 2 c data bus.
? 6 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a symbol exlc xlc extal xtal rst mp v dd vss input output input output i/o input clock oscillation i/os for crt display. oscillation frequency is set using the external l and c. crystai connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. low-level active, system reset. rst is an i/o, from whlch low level is output when the built-in power-on reset function is activated at the rise of power on. (mask option) microprocessor mode input. for this device, this pin must be grounded. vcc supply. gnd. both vss must be grounded. i/o description
? 7 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a d a t a b u s r d ( p o r t d ) a a a a i p a a a a a a a a p o r t d d i r e c t i o n a a a a p o r t d d a t a h i g h c u r r e n t 1 2 m a s c h m i t t i n p u t s c k o n l y s c k o r s o o u t p u t e n e b l e d a t a b u s r d ( p o r t s a , b , a n d c ) a a a a i p a a i n p u t p r o t e c t i o n c i r c u i t a a a a a a a a d a t a f o r p o r t s a , b , a n d c a a a a a a a a a a a a d i r e c t i o n f o r p o r t s a , b , a n d c d a t a b u s r d ( p o r t d ) a a a a i p a a a a a a a a a a a a p o r t d d i r e c t i o n a a a a a a a a p o r t d d a t a h i g h c u r r e n t 1 2 m a i n t 2 , s i , h s i , a c i , r m c , e c s c h m i t t i n p u t port d 2 pins pd1/sck pd2/so input/output circuit formats for pins port a port b port c port d 24 pins 6 pins hi-z hi-z hi-z pin when reset circuit format pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0/int2 pd3/si pd4/hsi pd5/aci pd6/rmc pd7/ec
? 8 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a a a a a i p r d ( p o r t e ) d a t a b u s s c h m i t t i n p u t ( t o i n t e r r u p t i o n c i r c u i t ) a a a a a a i p i n p u t m u l t i p l e x e r t o a / d c o n v e r t e r r d ( p o r t e ) d a t a b u s a a a a t o , p w m a a a a a a a a p o r t s e l e c t i o n a a a a a a a a p o r t e d a t a port e 2 pins 4 pins 2 pins pin when reset circuit format pe0/int0 pe1/int1 port e port e high level hi-z hi-z pe2/an0 to pe5/an3 pe6/pwm pe7/to s c l , s d a a a a a a a a a p o r t s e l e c t i o n a a a a a a a a a a a a p o r t f d a t a p w m i 2 c o u t p u t e n a b l e a a a a i p s c h m i t t i n p u t s c l , s d a ( t o i 2 c c i r c u i t ) t o o t h e r i 2 c p i n s b u s s w p w m a a a a a a a a a a p o r t s e l e c t i o n a a a a a a a a a a a a a a p o r t f d a t a m i d d l e t e n s i o n p r o o f 1 2 v h i g h c u r r e n t 1 2 m a port f port f 4 pins 4 pins pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 hi-z hi-z pf0/pwm0 to pf3/pwm3
? 9 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a 4 pins 2 pins pin when reset circuit format hi-z oscillation terminated blk r g b exlc xlc a a b l k , r , g , b h i - z ? o u t p u t a c t i v e b y w r i t i n g i n t o t h e o u t p u t p o l a r i t y r e g i s t e r . a a a a a a a a o u t p u t p o l a r i t y 2 pins hi-z hsync vsync h s y n c v s y n c a a a a a i p s c h m i t t i n p u t a a a a a a a a i n p u t p o l a r i t y o s c i l l a t i o n c o n t r o l a a a a e x l c a a a a i p c r t d i s p l a y c l o c k a a i p x l c a a a a 2 pins 1 pin rst oscillation low level extal xtal a a a a a a i p a a a a e x t a l x t a l d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p . a a a a f r o m p o w e r - o n r e s e t c i r c u i t m a s k o p t i o n s c h m i t t i n p u t p u l l - u p r e s i s t a n c e o p ( m a s k o p t i o n ) 1 pin mp hi-z a a a a i p c p u m o d e
? 10 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a * 1 v in and v out must not exceed v dd + 0.3v. * 2 the high current operation transistor is the n-ch transistor of pd and pf0 to pf3. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium voltage drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd v in v out v outp i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +15.0 ? ?0 15 20 130 ?0 to +75 ?5 to +150 1000 600 v v v v ma ma ma ma ma c c mw mw pins pf0 to pf3 total for all output pins excludes high current outputs high current outputs * 2 total for all output pins sdip qfp symbol rating unit remarks absolute maximum ratings (vss = 0v reference) supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range low-speed mode guaranteed operation range * 1 guaranteed data hold range during stop includes i 2 c schmitt input * 2 cmos schmitt input * 3 extal * 4 includes i 2 c schmitt input * 2 cmos schmitt input * 3 extal * 4 v dd * 1 specifies only for 1/16 frequency demultiplication mode and sleep mode. * 2 value for each pin of normal input ports (pa, pb, pc, pe2 to pe5), pf4 to pf7, and mp. * 3 value of the following pins: pd0/lnt2, pd1/sck, pd2, pd3/sl, pd4/hsl, pd5/aci, pd6/rmc, pd7/ec, pe0/int0, pe1/lnt1, hsync, vsync, rst. * 4 specifies only during external clock input. recommended operating conditions (vss = 0v reference) item
? 11 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 4.5v, i ol = 12.0ma high level output current low level output current input current i/o leakage current open drain output leakage current ( n-ch tr in off state) impedance connected to i 2 c bus switch ( output tr in off state) power supply current input capacity 4.0 3.5 8 0.5 10 2 20 a pf 20 50 10 120 ma ma a a 0.4 0.6 1.5 0.4 0.6 40 ?0 ?00 10 v v v v v a a a a 0.5 ?.5 ?.5 v v pa to pd, pe6, pe7, r, g, b, blk pa to pd, pe6, pe7, r, g, b, blk, pf0 to pf3, rst * 1 pd, pf0 to pf3 pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst * 2 pa to pe, hsync, vsync, r, g, b, blk, rst * 2 , mp pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd * 3 operation mode * 3 (1/2 frequency demultiplier clock) 4mhz crystal oscillation (c 1 = c 2 = 22pf) all outputs open stop mode * 4 sleep mode pins other than v dd and vss clock 1mhz 0v for all pins excluding item symbol pins conditions min. typ. max. unit v oh v ol i iz i loh r bs i dd i ddsl i ddst c in i ihe i ihl i ilr electrical characteristics dc characteristics (ta = ?0 to +75 c, vss = 0v reference) * 1 rst specifies only when the power-on reset circuit has been selected througn mask option. * 2 rst specifies input current when the pull-up resistance has been selected; ieakage current when no resistance has been selected. * 3 specifies only when the oscillatlon of osd has been terminated. * 4 this device does not enter the stop mode.
? 12 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a ac characteristics (1) clock timing * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") system clock frequency system clock input pulse width system clock input rise time, fall time event clock input clock pulse width event count input clock rise time, fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec mhz ns ns ns ms item symbol pins conditions min. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 4.5 200 20 3.5 100 t sys + 50 * 1 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c fig. 2. clock applying condition a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l o p e n c 1 c 2 fig. 3. event count clock timing e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d
? 13 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a (2) serial transfer (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time symbol pins conditions min. max. unit note) the load condition for the sck output mode, so output delay time is 50pf + 1ttl. fig. 4. serial transfer timing 0 . 2 v d d 0 . 8 v d d t k l t k h s o t k c y t s i k t k s i 0 . 2 v d d 0 . 8 v d d t k s o 0 . 2 v d d 0 . 8 v d d o u t p u t d a t a i n p u t d a t a s i s c k
? 14 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a external interruption high and low level widths reset input low level width int0 to int2 rst 1 8/fc s s item symbol pins conditions min. max. unit t ih t il t rsl power supply rise time power supply cut-off time t r t off v dd power-on reset repetitive power-on reset 0.05 1 50 ms ms item symbol pins conditions min. max. unit (3) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) (4) power on reset power on reset * (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 t o i n t 2 ( f a l l i n g e d g e ) 0 . 2 v 0 . 2 v 4 . 5 v v d d t r t o f f t h e p o w e r s u p p l y s h o u l d b e r a i s e d s m o o t h l y . fig. 5. interruption input timing t r s l 0 . 2 v d d r s t fig. 6. rst input timing fig. 7. power-on reset * specifies only when the power-on reset function has been selected.
? 15 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt * 1 v ft * 2 t conv t samp v ian an0 to an3 ta = 25 c v dd = 5.0v vss = 0v ?0 4370 160/fc 12/fc 0 160 4530 4 1 320 4690 v dd bits lsb mv mv s s v item symbol pin condition min. typ. max. unit (5) a/d converter characteristics (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) l i n e a r i t y e r r o r v z t v f t a n a l o g i n p u t f h e h 1 h 0 h d i g i t a l c o n v e r s i o n v a l u e fig. 8. definition of a/d converter terms * 1 v zt : value at which the digital conversion value changes from 0 h to 1 h and vice versa. * 2 v ft : value at which the digital conversion value changes from e h to f h and vice versa. note) the 4-bit conversion specifies values based on the upper 5 bits of the a/d data register (add: address 00f5 h ), compensated into 4-bit data. a program example is shown below: (a/d converter program example) mov a, add ; acc ? conversion data lsr a ; shift to the right (4 times) lsr a ; lsr a ; lsr a ; adc a, #00h ; addition with carry (data increment if ad3 = 1) cmp a, #10h ; bne adc_skip ; mov a, #0fh ; adc_skip:
? 16 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a (6) i 2 c bus timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus free time prior to transfer start transfer start hold time clock low level width clock high level width setup time during repetitive transfer data hold time data setup time sda, scl rise time sda, scl fall time transfer end setup time f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 1 250 4.7 100 1 300 khz s s s s s s ns s ns s symbol pins conditions min. max. unit * 1 the data hold time does not take into consideration scl rise time (300ns max.). ensure that the data hold time exceeds 300ns. fig. 9. i 2 c bus transfer timing p s t t s u ; s t o t s u ; s t a t h d ; s t a t s u ; d a t t h i g h t h d ; d a t t f t r t l o w t h d ; s t a s p t b u f s d a s c l fig. 10. recommended circuit example for i 2 c device i 2 c d e v i c e i 2 c d e v i c e r s r s r s r s r p r p s d a 0 ( o r s d a 1 ) s c l 0 ( o r s c l 1 ) pull-up resistors (r p ) must be connected to sda0 (or sda1) and scl0 (or scl1). serial resistance (rs = 300 and under) of sda0 (or sda1) and scl0 (or scl1) reduces spike noise caused by crt flashover.
? 17 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a (7) osd (on-screen display) timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item osd clock frequency hsync pulse width vsync pulse width hsync after-edge rise time/fall time vsync after-edge rise time/fall time f osc t hwd t vwd t hcg t vcg exlc xlc hsync vsync hsync vsync fig. 12 fig. 11 fig. 11 fig. 11 fig. 11 4 1.2 1.0 13 200 1.0 mhz s h* ns s symbol pins condition unit min. max. fig. 11. osc timing 0 . 8 v d d 0 . 2 v d d t h c g t h w d h s y n c w h e n b i t 5 o f o p o l r e g i s t e r ( 0 1 f b h ) i s s e t t o " 0 " 0 . 8 v d d 0 . 2 v d d t v c g v s y n c w h e n b i t 4 o f o p o l r e g i s t e r ( 0 1 f b h ) i s s e t t o " 0 " t v w d fig. 12. lc oscillation circuit example l c 2 c 1 e x l c x l c * h indicates 1hsync period.
? 18 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a 4.00 4.19 4.00 4.19 4.00 4.19 4.00 4.19 supplement c 2 c 1 a a a a a a a a a a a a a a a e x t a l x t a l r d a a a a a a a a a a a a a a a e x t a l x t a l r d ( i ) a a a a a a a a a a a a a a a e x t a l x t a l c 1 c 2 r d x t a l ( i i ) manufacturer murata mfg co., ltd. kinseki ltd. model csa4.00mg csa4.19mg cst4.00mgw * cst4.19mgw * hc-49/u03 hc-49/u (-s) fc (mhz) 30 30 0 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (ii) (i) 10 18 10 18 0 * indicates types with on-chip grounding capacitance (c 1 and c 2 ). river eletec corporation item content reset pin pull-up resistance power-on reset circuit non-existent non-existent existent existent mask option table fig. 13. recommended oscillation circuit
? 19 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a fig. 14. characteristics curves i d d v s . v d d ( f c = 4 m h z , t a = 2 5 c t y p i c a l ) 1 5 1 0 1 0 . 1 2 3 4 5 6 v d d s u p p l y v o l t a g e [ v ] i d d p o w e r s u p p l y c u r r e n t [ m a ] 1 / 2 f r e q u e n c y d e m u l t i p l i c a t i o n m o d e 1 / 4 f r e q u e n c y d e m u l t i p l i c a t i o n m o d e 1 / 1 6 f r e q u e n c y d e m u l t i p l i c a t i o n m o d e s l e e p m o d e 1 2 1 f c s y s t e m c l o c k [ m h z ] i d d p o w e r s u p p l y c u r r e n t [ m a ] 1 / 2 f r e q u e n c y d e m u l t i p l i c a t i o n m o d e 1 / 4 f r e q u e n c y d e m u l t i p l i c a t i o n m o d e 1 / 1 6 f r e q u e n c y d e m u l t i p l i c a t i o n m o d e s l e e p m o d e 1 1 1 0 9 8 7 6 5 4 3 2 1 0 2 3 4 5 6 o s d o s c i l l a t i o n v s . c c a l c u l a t e d c u r v e s ( r e f e r e n c e v a l u e b y t h e o r e t i c a l c a l c u l a t i o n ) 1 0 0 1 0 1 0 5 0 1 0 0 1 3 . 0 m h z 6 . 5 m h z l i n d u c t a s c e [ h ] c 1 , c 2 c a p a c i t a n c e [ p f ] i d d v s . f c ( v d d = 5 v , t a = 2 5 c t y p i c a l ) f o s c = c = c 1 / / c 2 2 p l c 1 5 . 0 m h z
? 20 cxp85112b/85116b, cxp85220a/85224a/85228a/85232a p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s s o n y c o d e e i a j c o d e j e d e c c o d e s d i p - 6 4 p - 0 1 4 2 a l l o y s o l d e r p l a t i n g e p o x y r e s i n 6 4 p i n s d i p ( p l a s t i c ) s d i p 0 6 4 - p - 0 7 5 0 5 7 . 6 0 . 1 + 0 . 4 6 4 3 3 1 3 2 1 . 7 7 8 1 9 . 0 5 1 7 . 1 0 . 1 + 0 . 3 0 t o 1 5 0 . 2 5 0 . 0 5 + 0 . 1 0 . 5 m i n 4 . 7 5 0 . 1 + 0 . 4 3 . 0 m i n 0 . 5 0 . 1 0 . 9 0 . 1 5 8 . 6 g s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p - 6 4 p - l 0 1 q f p 0 6 4 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0 0 t o 1 0 package outline unit: mm

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